The present invention relates to a semiconductor memory device and particularly to a method for arranging power supply lines which are laid out so as to ensure that each memory element conducts sensing operations at high speed.
The more highly a semiconductor memory device is integrated, the greater the problem achieving high-speed operations. It is widely known in this field that sensing operations of a bit line must be conducted at a high speed rate for high-speed operations of a chip. However, the more highly a semiconductor memory device is integrated, the chip increases in size and a metal layer covering a memory array decreases in width. This causes its metal wiring resistance to grow and results in lowering its high-speed operations. Particularly, the resistance of the power supply lines which are connected between memory cells and a power supply voltage terminal and a ground voltage terminal is great considerably, and it is so directly related to lowering sensing speed that the study of the power supply line layout is now prosecuted earnestly.
The conventional memory array power supply line layout is illustrated in FIGS. 1A to 1D.
FIG. 1A takes a 1-Mega dynamic random access memory (DRAM) as an example. The memory is divided into a memory cell array area 10 and a periphery area 10'. A pull-up driver 2 for sensing is connected to a Vcc-pad to which a power supply voltage is applied; and a pull-down driver 1 for sensing is connected to a Vss-pad to which a ground voltage is applied. A plurality of memory cell sensing blocks 5 are in the memory cell array area 10, and the Vcc-pad and the Vss-pad are connected to the memory cell sensing blocks 5. In this case, a line connected to the Vcc-pad is called the power line and a line connected to the Vss-pad is called the ground line. The power and ground lines are commonly called the power supply line.
FIG. 1B takes a 4-Mega DRAM as an example. The memory is similar to FIG. 1A, having one difference from FIG. 1A in that the pull-down drivers for sensing 11, 12 are disposed in each sense amplifier within the memory cell array area 20.
FIG. 1C takes a 16-Mega DRAM as an example. Pull-up and pull-down drivers for sensing are within the memory cell array area. It is aptly shown in FIG. 1C which is a partially detailed view of block 18 in FIG. 1D. A column select line CSL for selecting a given corresponding column, a word line strap area are shown in FIG. 1C.
Now, the characteristics of FIGS. 1A to 1D will be described hereinafter.
In the case of 1-Mega DRAM in FIG. 1A, the pull-up and pull-down drivers 2, 1 for sensing are disposed in the periphery area 10' so that the power and ground lines 4, 3 respectively have a considerable amount of resistances R1, R2 and R3, R4 in the memory cell array area 10.
In the case of 4-Mega DRAM which is improved from the 1-Mega DRAM, as illustrated in FIG. 1B, a pull-up driver 13 for sensing is disposed in a periphery area 20' and the pull-down drivers 11, 12 for sensing is disposed in each sense amplifier within the memory cell array area 20 but, as a power line is and a ground line, 14 respectively connected to each driver 11, 12 are each a single path, there is a limit in reducing resistances R5, R7, R8, . . . , etc.
In the case of 16-Mega DRAM as illustrated in FIGS. 1C and 1D, since a pull-up and pull-down drivers 22, 21 for sensing separately is disposed in each word line strap area (which is possible because the width of word line strap area becomes relatively larger by a improvement of design rule), resistance between each sense amplifier 23 and the pull-up and pull-down drivers 22, 21 for sensing is thereby reduced to a considerable degree. However, as it is possible to connect the pull-up and pull-down drivers 22, 21 for sensing to each power supply line only in the word line strap area where there are several power supply lines, there is a limit in reducing total resistance. As illustrated in FIG. 1D, the column select lines CSL which select a column of memory cell within block 17 are so situated as to be adjacent to each other that it leads to erroneous operations by causing a coupling phenomenon between the column select lines CSL.